The present disclosure relates generally to static random access memory (SRAM) devices and, more specifically, to an SRAM device having a high aspect ratio cell boundary.
The physical dimension of a feature on a chip is referred to as “feature size.” Reducing the feature size on a chip permits more components to be fabricated on each chip, and more components to be fabrication on each silicon wafer, thereby reducing manufacturing costs on a per-wafer and a per-chip basis. Increasing the number of components in each chip can also improve chip performance because more components may become available to satisfy functional requirements.
SRAM devices are one type of device that may undergo such scaling to reduce manufacturing costs. SRAM is random access memory that retains data bits in its memory as long as power is being supplied. Unlike dynamic random access memory (DRAM), SRAM does not have to be periodically refreshed. SRAM also provides faster access to data than DRAM. Thus, for example, SRAM is frequently employed in a computer's cache memory, or as part of the random access memory digital-to-analog converters in video cards.
However, SRAM is more expensive than other types of memory. Thus, SRAM designers and manufacturers continually strive to reduce the costs of manufacturing SRAM devices. The scaling of features sizes discussed above is one of the means to achieve such cost reduction. However, scaling feature sizes is not the only means available to reduce SRAM manufacturing costs. For example, modifying the layout of features within an SRAM chip to further increase the packing density of SRAM cells within each chip can also reduce manufacturing costs.
Accordingly, what is needed in the art is an SRAM device and method of manufacture thereof that addresses the above discussed issues.